Abstract: In the process of testing VLSI circuits, it is required to test the entire operation with minimum all patterns. However for complete fault analysis total test patterns derived were quite large. This large number of coefficient representation results in large time of testing and hence consumes more power for testing operation. It is required to optimize this power consumption, based on the pattern optimization. In the approach of pattern optimization, state skip modeling was proposed in recent. In such coding approach, the process of pattern optimization using LFSR optimization was developed. In this paper a optimization of test patterns based on block switch modeling is proposed. The approach of pattern alignment using a synonymous approach of genetic mutation is proposed. The test evaluation of the suggested work is carried over ISCAS 89 benchmark circuits. The fault tolerance, recursion overhead, and logical implementation are observed to be optimized for the proposed approach.

Keywords: Test Pattern optimization, Genetic coding, built in self test, Block mutation .