Abstract: Due to the excellent error control performance in many communication systems Convolution encoder and Viterbi decoder are widely used. In coding techniques the number of symbols in the source encoded message is increased in a controlled manner in order to facilitate two basic demand at the receiver one is Error detection and other is Error correction. The amount of error detection and correction required and its efficiency depends on the signal to noise ratio (SNR). The technology based on Non Line of Sight (NLOS) ability to make the system very attractive for users, but there will be a little higher BER at low SNR. Coding is a technique where redundancy is added to original bit sequence to increase the reliability of the communication. This paper presents a review on hardware implementation of Convolution Encoder with power efficient architecture. The results of this architecture will decrease the dynamic power and HW cost with lower design complexity as comparing to conventional method.
Keywords: Automatic Repeat Request (ARQ), Forward Error Correction (FEC), Convolutional Code (CC), Non Line of Sight (NLOS).