Abstract: Industry is approaching towards complete system-on-chip (SoC) design solutions that include power management. Power has become one of the most important part of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. Hence by using 45nm CMOS technology parameters PLL is designed. This gives at low power consumption high speed performance. MOS model called BSIM4 recommended for ultra-deep submicron technology simulation. The Software Tanner13.0 tool used to allows designing and simulating an integrated circuit at physical description level. Today’s communication systems, processors and computing devices require circuit of low power consumption, small size, high speed and low fabrication cost for these requirements to design PLL by using 45nm CMOS technology. The main objective of PLL is to generate signal in which phase of feedback signal is same as phase of reference signal. This is achieved after many iteration of comparison of the reference and feedback signal.  One of them is XOR gate based detection but it is less preferred as compared to the PFD. The reason behind rejecting use of XOR gate as detector was that that it can lock onto harmonics of the reference signal and most important it cannot detect a difference in frequency. These disadvantages were overcome by other type of PFD.

 Keywords: Phase Lock Loop (PLL), Phase Frequency Detector (PFD), 45nm CMOS Technology, Tanner13.0

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