Abstract-Gate Diffusion Input-(GDI) is a novel technique for low power digital VLSI circuits to reduce the powerdissipation, propagation delay and transistor count thereby reducing the size and the area occupied by the circuit on the chip.

The conventional GDI technique suffers from the voltage degradation problem. This paper presents a modified version of the GDI technique where a strong logic 1 as well as strong logic 0 is obtained. Using the Modified-GDI technique adders like RCA along with fast adders such as Carry Skip adder and Carry Look Ahead adders are built and simulated using 130nm technology. The results obtained for the Modified GDI based adders are compared with the conventional Complementary CMOS RCA, CSA and CLA adders. It is found that using the Modified GDI technique there is a significant (i.e. 45%) reduction in the power dissipation for basic 4-bit CLA adder, along with reduction in the transistor count and less propagation delay (i.e. 20%) in the RCA when using GDI Technique. The simulation is carried out in the Electric Software and LT-Spice VLSI EDA CAD tool with SPICE BSIM3 model file.


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