A NOVEL LOGIC STYLE USED FOR LEAKAGE POWER REDUCTION IN MOS INTEGRATED CIRCUIT

Abstract: Full adders are necessary parts in applications corresponding to digital signal processors (DSP) architectures and microprocessors. Additionally to its main task, that is adding 2 numbers, it participates in several different helpful operations appreciate subtraction, multiplication, division, address calculation, etc. In most of those systems the adder lies in the critical path that determines the general speed of the system. Therefore enhancing the performance of the 1-bit full adder cell (the building block of the adder) could be a significant goal. Demands for the low power VLSI approaching the expansion of insistent design process to control use severely. To accomplish the rising demand, we advise a new low power adder by give up the MOS transistor calculate that reduce the grave threshold defeat so anew enhanced 14T CMOS l-bit full adder cell is specified in this paper. Results show five hundredth improvement in threshold loss drawback, 45% improvement in speed and considerable power consumption over the given adder and other different types of adders with comparable presentation.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).