Design and Analysis of Digitally Trimmable Sub – Bandgap Reference in CMOS Technology

Abstract: This paper presents the design and implementation of a low-power digitally trimmable CMOS bandgap reference (BGR) circuit intended for high-precision and temperature-stable voltage reference generation in modern VLSI systems. The performance of conventional bandgap reference circuits is significantly affected by process variations, device mismatch, and temperature fluctuations, resulting in reduced output accuracy and long-term stability. To address these limitations, a digitally controlled trimming architecture employing a binary-weighted resistor array integrated with CMOS switching logic is proposed. The trimming network enables fine adjustment of the reference voltage and compensates for fabrication-induced variations, thereby enhancing the overall circuit accuracy and thermal stability. The proposed BGR circuit is designed with emphasis on low power dissipation, compact implementation, and reliable operation over a wide temperature range. Detailed simulation analysis is carried out to evaluate key performance parameters including reference voltage stability, temperature coefficient, line sensitivity, and power consumption under varying operating conditions. Simulation results demonstrate that the proposed digitally trimmable architecture achieves improved voltage precision and reduced temperature dependency when compared with conventional CMOS bandgap reference circuits, making it suitable for low-power analog and mixed- signal integrated circuit applications.

Keywords: Bandgap Reference (BGR), CMOS Technology, Digital Trimming, Low Power VLSI, Voltage Reference Circuit, Binary-Weighted Resistor Array, Temperature Compensation, Analog Integrated Circuits, Process Variation, Low Power Design, CMOS Switches, Mixed-Signal IC Design.