Design and Circuit-Level Analysis of Low-Power Analog Neural Networks in CMOS Technology

Abstract: This paper presents the circuit-level design and performance analysis of a low-power Analog Neural Network (ANN) implemented in standard CMOS technology, targeting energy-constrained biomedical and edge-AI VLSI applications. The proposed architecture realises ANN inference entirely in the continuous-time analog domain using four principal circuit primitives: a Current Correlator (CC), an Adaptive Differential Equaliser (ADEL), a Gaussian Activation Function Circuit, and a Synaptic Function Circuit (SFC). All circuits are designed and characterised in Cadence Virtuoso. Simulation results confirm a peak-to-peak differential voltage gain of 2.928×, a −3 dB bandwidth of 15.89 GHz, and near-unity Gaussian voltage transfer (gain ≈ 1.000) with a current gain of 1.266× under low-supply conditions. Comprehensive transient, DC, and AC analyses validate stable, linear operation across the expected operating range. The work establishes a quantitative performance baseline for future integration of SFC and comparator stages toward a fully functional on-chip analog ANN classifier.

Keywords: Analog Neural Network, CMOS VLSI, Low-Power Design, Current Correlator, ADEL, Gaussian Activation Function, Synaptic Function Circuit, Cadence Simulation, Sub-threshold Operation, Edge AI.