DESIGN OF 32-BIT UT MULTIPLIER USING REVERSIBLE LOGIC AND COMPARISON WITH DIFFERENT ADDERS: A VEDIC MATHEMATICAL APPROACH

Abstract: Multipliers are vital components of any processor or computing machine. Performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time.To enhance speed many modifications over the standard modified booth algorithm, Wallace tree methods for multiplier design have been made and several new techniques are being worked upon. Amongst these Vedic multipliers based on Vedic mathematics are presently under focus due to these being one of the fastest and low power multiplier. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution and has better results. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this project we bring out a Vedic multiplier known as "Urdhva Tiryakbhayam"meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

Keywords: Vedic Multiplier, Reversible Logic, Urdhva Tiryakbhayam, Ripple carry adder, Carry select linear adder, BEC-1 adder.