DESIGN OF PARALLEL ADDER/SUBTRACTOR USING A NOVEL REVERSIBLE LOGIC GATE

Abstract: Reversibility plays an important role when energy efficient computations are considered Parity preserving property can be used for this. Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy Ribonucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem a new 5*5 parity preserving reversible gate is proposed in this paper, named as P2RG. The most significant aspect of this work is that it can work both as a full adder and a full subtractor by using one P2RG and Fredkin gate only. According to the control logic input the proposed design can works as an adder or a subtractor.

Keywords: (De Oxy Ribonucleic Acid) DNA, (Complementary Metal Oxide Semiconductor) CMOS design, P2RG.