FPGA Based Low-Power and Area-Efficient 4- bit Arithmetic Logic Unit

Abstract: Arithmetic Logic Units (ALUs) are fundamental components of digital processors and embedded systems, responsible for executing arithmetic and logical operations with high speed and reliability. As modern FPGA-based systems increasingly target portable, real-time, and energy-constrained applications, designing ALUs with reduced power consumption and optimized hardware utilization has become a critical research objective. This paper presents an FPGA- Based Low-Power and Area-Efficient 4-bit Arithmetic Logic Unit (LPAE-4ALU) that achieves improved energy efficiency while maintaining high computational performance. The proposed architecture integrates optimized combinational logic with an efficient operation selection mechanism to minimize switching activity and reduce logic resource utilization. The ALU supports essential arithmetic operations, including addition, subtraction, increment, and decrement, along with logical operations such as AND, OR, XOR, NOT, NAND, NOR, and XNOR. The design is implemented using Verilog HDL and synthesized on a Xilinx FPGA platform to evaluate its performance in terms of lookup table (LUT) utilization, flip-flop usage, operating frequency, propagation delay, and power consumption. Experimental results demonstrate that the proposed architecture achieves lower dynamic power consumption and reduced hardware area compared with conventional 4-bit ALU implementations while maintaining accurate functionality and high-speed operation. The proposed LPAE-4ALU is therefore well suited for low-power embedded processors, Internet of Things (IoT) devices, digital signal processing systems, and FPGA-based System-on-Chip (SoC) applications.

Keywords: 4-bit Arithmetic Logic Unit (ALU), FPGA Implementation, Low-Power Design, Area Optimization, Verilog HDL.