Abstract: Hardware security gets involved in various operations and they are in the field of e-commerce, banking, communications, satellite, image processing and so on. Cryptography is nothing but it is the procedure of transforming the plain input text into the cipher output or vice versa. Three forms of Cryptography: Private Key Cryptography, Public Key Cryptography & Hash functions. Private Key is nothing but it makes use of a similar key for Encryption & also for Decryption process whereas Public Key is nothing but it uses the two different keys for encryption and also for decryption process. Since AES operates using similar key for Encryption as well as Decryption so this type performance are important hastily, easy to apply and it requires truly lower processing power. Encryption process is only thing left to guard the specific information or data communication. Depending on the Key length it’s more effective and there are three Key lengths options available and they are 128bit, 192bit and 256bit pivotal length. Greater the Key length more time is demanded to break the system or to hack the system. AES performs four different functions or transformations and they are as follows: Sub-bytes, Shift-rows, and Mix-column & Add round Key. By using Pipelined Architecture and LUT greater speed can be achieved. The proposed architecture is formed on optimizing timing and this is done by using verilog HDL.

Keywords: AES (Advanced Encryption Standard), FPGA (Field Programmable Gate Array), LUT (Look Up Table), Mix (Mix-column) Shift (Shift-rows), Sub (Sub-bytes).

| DOI: 10.17148/IARJSET.2022.9755