IMPLEMENTATION OF HIGH SPEED 32- BIT CARRY SKIP ADDER USING CONCATENATION AND INCREMINATION LOGIC

Abstract: In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incremination schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. The speed improvement was achieved by using variable size blocks; parallel prefix adders in the nucleus stage finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed. CI-CSKA has been synthesized using the XILINX ISE DESIGN SUITE 14.3 tool for Spartan3E family, the XC3S500E device with a speed grade of -5. Simulations on the variable latency CSKA show on average of 40% improvement in the delay.

Keywords: Carry skips adder (CSKA), energy efficient, high performance, hybrid variable latency adders, concatenation and incrementation (CI-CSKA).