Implementation on “Area-Delay-Power Efficient Carry-Select Adder”

Abstract: In this paper, we made an analysis on the logic operations involved in conventional carry select adder (CSLA) and CSLA based on binary to excess-1 converter (CSLA-BEC) to study the data-dependency, and to find redundant logic operations. We have eliminated all the redundant logic operations of conventional CSLA, and proposed a logic formulation for CSLA. In the proposed scheme, the carry-select operation is scheduled before the calculation of final- sum, which is different from the conventional approach. To optimize the logic units, an efficient design is obtained for CSLA. Due to small carry-output delay, the proposed CSLA design is a good candidate for SQRT adder.

Keywords: Adder, BEC, Low power design, CSLA