Abstract: Multiplier is one of the key blocks in most of the high performance and digital systems such as the microprocessors, digital signal processors & FIR filters. This paper presents a model of 8-bit multiplier i.e. Radix -8 booth Wallace multiplier using common Boolean logic. Radix 8 Booth algorithm is responsible to generate the partial products. Wallace tree structure using 3:2 compressors is responsible for the reduction and accumulation of partial products to two rows. Whereas the SQRT
[stumble] CSLA with Common Boolean logic is responsible to add the last two rows of partial products. The use of compressors in Wallace tree structure and common Boolean logic in the adder results in the reduction of overall delay and power consumption of the multiplier. A Verilog code has been written which is synthesized in Xilinx ISE 14.7 software and simulated in ModelSim. After simulation the performance of this multiplier is compared with the modified booth wallace multiplier using carry save adder & is found that the power and delay of the proposed multiplier is reduced with the increase in the number of gate count.

Keywords: Booth Encoder, Wallace tree, Compressors, MSQRT CSLA, CBL.

| DOI: 10.17148/IARJSET.2021.81241