SQRT Carry Select Adder with Efficient Area Delay Product Using VHDL Architecture

Abstract: Reduced area, delay and power dissipation are the main factors that play an important role in the increasing demand of electronic devices. Adders have a great role in computing arithmetic unit. In the proposed adder design, new logic formulation is proposed by analysing the existing methods thereby reducing the redundant logic operations and data dependency. The probable carry-in (either cin = 0 or cin =1) from the previous Carry Select Adder (CSLA) decides the original sum and carry out. Here, the carry is scheduled before the sum generation. Thus the proposed system experiences small carry output delay. Low area efficient and delay efficient design is implemented. Thus the proposed SQRT CSLA can replace the existing CSLA designs. Keywords: Adder, Arithmetic Unit, Carry Select Adder, Delay Efficient