Abstract: The growing demand for energy-efficient and high-performance arithmetic units in digital systems has intensified research into low-power design techniques. Adders, being fundamental components in digital signal processing, multimedia, and machine learning applications, play a crucial role in overall system performance. This project presents a hybrid power and area efficient parallel prefix adder (PPA) design that utilizes approximate computing to reduce power and area consumption, while maintaining acceptable accuracy levels for error-tolerant applications. The proposed architecture divides the adder into two distinct sections: the Least Significant Part (LSP), which employs approximate logic to reduce complexity and resource usage, and the Most Significant Part (MSP), which retains exact computation to ensure result fidelity where it is most critical. A combination of Kogge-Stone and radix-4 adder structures is used to balance speed, architectural simplicity, and energy savings. The design introduces approximate prefix operators (AxPOs) that eliminate or simplify certain logic gates in the carry propagation paths, significantly optimizing power and delay. Four approximate PPA variants—AxPPA-BK (Brent-Kung), AxPPA-KS (Kogge-Stone), AxPPA-LF (Ladner-Fischer), and AxPPA-SK (Sklansky)—are developed and evaluated against the proposed hybrid adder. The implementation is carried out in Verilog HDL, simulated using ModelSim, and synthesized using Xilinx ISE. Comparative analysis shows that the hybrid adder achieves notable reductions in power, area, and delay compared to traditional PPAs and other approximate designs, making it a compelling solution for power-constrained systems in approximate computing domains.

Keywords: Approximate Adder, Kogge-Stone Adder, Ladner-Fischer Adder, Parallel Prefix Adder (PPA), Brent-Kung Adder, Sklansky Adder.

Downloads: | DOI: 10.17148/IARJSET.2025.12756