Abstract: The Multiply-Accumulate (MAC) unit plays a pivotal role in digital signal processing (DSP), image processing, and embedded applications, where speed and power efficiency are of utmost importance. This paper proposes a novel 32-bit MAC architecture employing a hybrid Vedic multiplier and reversible logic gates, integrated with a Han-Carlson adder to enhance computational performance. The hybrid multiplier combines the advantages of traditional and Vedic techniques for faster partial product generation, while the use of reversible logic gates significantly reduces power dissipation, making the design suitable for low-power applications. The Han-Karlson adder, with its high-speed carry propagation and balanced logic structure, further accelerates the addition process. The proposed design is modelled and simulated using industry-standard tools and is evaluated against conventional MAC architectures in terms of delay, area, and power. Experimental results confirm that the proposed MAC unit achieves superior performance, offering a viable solution for next-generation VLSI systems.

Index terms: Multiply-Accumulate Unit (MAC), Vedic Multiplier, Reversible Logic Gates, Han-Karlson Adder, Low Power, High Speed, VLSI Design, Digital Signal Processing.

| DOI: 10.17148/IARJSET.2025.12502