Abstract: Reversible logic is one of the most promising technology of the future computation, owing to its capability to tremendously reduce the dissipation of power. It has got extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata, ultra-low power VLSI circuits, advanced computing, DNA computing, Bio informatics and Nano technology. Since multipliers are one of the prominent building blocks of most of the computational units and since the speed of the computational units is largely determined by the speed of the multipliers, hence in order to increase the speed of computational units, we need to utilize faster multipliers. This is where Urdhva Tiryakbhayam (UT) Vedic multiplier comes into play. This multiplier performs the multiplication operation at a tremendously increased speed as compared to conventional multipliers, with decreased delay. This multiplier can be efficiently used in Digital signal processing system, Fast Fourier Transforms (FFTs), Filter design, Image processing and in other fast computational units including ALU. Thus we utilize the low power capability of reversible logic to reduce power dissipation and the high speed capability of Vedic multipliers to speed up the operation in our design. In this paper, we have shown the implementation of 4 different design architectures of Vedic multipliers using reversible logic which are optimized in terms of area, delay, power consumption and total computational complexity including quantum cost of the design. The design has been implemented on the Xilinx ISE Design Suite 14.7 using Verilog. The results of the analysis of all the 4 architectures with its computational complexity has been presented.

Keywords: Reversible logic, Garbage output, Quantum cost, Reversible multiplier, Vedic multiplier, Urdhva Tiryakbhayam Sutra, Reversible logic gates, UT Multiplier, Quantum computing.

| DOI: 10.17148/IARJSET.2020.7310