Abstract: In this paper, we made an analysis on various clock distribution networks (CDN) and algorithms which are used to reduce the clock skew in the circuits to study the various delays associated in the circuit and also the clock parameters which we need considered. Some of the CDN concepts emphasize on the distance of the clock buffers from the clock source in order to reduce the clock skew by maintaining clock sinks at same distances from the clock source and some of the CDN concepts involve algorithms which help in developing a clock network which supplies clock to the clock buffers which are already placed at a certain positions and some of the concepts also involve delay models (such as Elmore delay model) in order develop a CDN with minimal clock skew. To study and as well as implement our proposed methodology which particularly emphasizes about clock skew we took the pipelining process into consideration to develop an efficient method to tackle the problems of clock skew, so in this paper we have also studied and made analysis on pipelining process. Many CDNs have reduced clock skew but not eliminated so we have proposed a methodology which helps in utilizing clock skew to increase the speed of the circuit.

Keywords: Clock, CDN, clock skew, clock buffer, pipelining.

| DOI: 10.17148/IARJSET.2021.86128