Phase Frequency Detector in Phase Lock Loop

+91-7667918914 iarjset@gmail.com 0 Items International Advanced Research Journal in Science, Engineering and Technology A Monthly Peer-Reviewed Multidisciplinary Journal ISSN Online 2393-8021 ISSN Print 2394-1588 Since 2014 Home About About IARJSET Aims and Scope Editorial Board Editorial Policies Publication Ethics Publication Policies Indexing and Abstracting Citation Index License Information Authors How can I publish my paper? Instructions to Authors Benefits to Authors Why Publish in IARJSET Call for Papers Check my Paper status Publication Fee Details Publication Fee Mode FAQs Author Testimonials Reviewers Topics Peer Review Current Issue & Archives Indexing FAQ’s Contact Select Page CETE-IARJSET 02 Abstract: Industry is approaching towards complete system-on-chip (SoC) design solutions that include power management. Power has become one of the most important part of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. Hence by using 45nm CMOS technology parameters PLL is designed. This gives at low power consumption high speed performance. MOS model called BSIM4 recommended for ultra-deep submicron technology simulation. The Software Tanner13.0 tool used to allows designing and simulating an integrated circuit at physical description level. Today's communication systems, processors and computing devices require circuit of low power consumption, small size, high speed and low fabrication cost for these requirements to design PLL by using 45nm CMOS technology. The main objective of PLL is to generate signal in which phase of feedback signal is same as phase of reference signal. This is achieved after many iteration of comparison of the reference and feedback signal. One of them is XOR gate based detection but it is less preferred as compared to the PFD. The reason behind rejecting use of XOR gate as detector was that that it can lock onto harmonics of the reference signal and most important it cannot detect a difference in frequency. These disadvantages were overcome by other type of PFD. Keywords: Phase Lock Loop (PLL), Phase Frequency Detector (PFD), 45nm CMOS Technology, Tanner13.0 Call for Papers Rapid Publication 24/7 April 2026 Submission: eMail paper now Notification: Immediate Publication: Immediately with eCertificates Frequency: Monthly Downloads Paper Format Copyright Form   Submit to iarjset@gmail.com or editor@iarjset.com   Submit My Paper Author CenterHow can I publish my paper? Publication Fee Why Publish in IARJSET Benefits to Authors Guidelines to Authors FAQs (Frequently Asked Questions) Author Testimonials IARJSET ManagementAims and Scope Call for Papers Editorial Board DOI and Crossref Publication Ethics Editorial Policies Publication Policies Subscription / Librarian Conference Special Issue Info ArchivesCurrent Issue & Archives Conference Special Issue Copyright © 2026 IARJSET This work is licensed under a Creative Commons Attribution 4.0 International License. Open chat