Abstract: This project presents the design and implementation of a single cycle RISC-V RV32I processor on FPGA using Xilinx ISE Design Suite. RISC-V is an open standard instruction set architecture that provides flexibility, scalability and privilege from proprietary constraints, making it an excellent choice for educational purposes. The processor is designed using Verilog HDL, includes essential components such as the instruction fetch, decode, execute, memory access and write-back stages.
The entire design is synthesized and implemented on a Spartan-6 FPGA board. This project demonstrates the feasibility and effectiveness of implementing a single cycle RISC-V processor on FPGA, providing valuable insights into processor design and hardware implementation.

Keywords: RISC-V single cycle processor design, RV32I Instruction Set, Spartan 6 FPGA, Xilinx ISE Design Suite.

| DOI: 10.17148/IARJSET.2024.11798