Design and Implementation of a 10-bit FSM based Digital SAR Logic in 90 nm CMOS Technology

Abstract: In mixed-signal systems, analog to digital converters (ADCs) are crucial for transforming analog signals into digital data. The Successive Approximation Register (SAR) ADC is one of the most popular ADC architectures because of its low power consumption, moderate resolution, and straightforward hardware design, which make it appropriate for Internet of Things applications, portable electronics, and biomedical devices. The control unit that completes the successive approximation process to produce the final digital output is the digital SAR logic.

In this work, a 10-bit Finite State Machine (FSM) based digital SAR logic using 90 nm CMOS technology is designed and implemented. The binary search conversion from the Most Significant Bit (MSB) to the Least Significant Bit (LSB) is carried out by the suggested architecture.

The Cadence digital design flow, which includes synthesis, timing analysis, power estimation, and physical design processes like floor planning, placement, routing, and GDSII generation, is used to create the design. The results show low power consumption and effective area utilization. For integration in low-power SAR ADCs used in biomedical, wireless sensor, and embedded data acquisition systems, the suggested FSM-based SAR logic provides a small and energy-efficient solution.

Keywords: Successive Approximation Register (SAR), Finite State Machine (FSM), Digital SAR Logic, Verilog HDL, 90 nm CMOS Technology, Low-Power VLSI Design, Analog-to-Digital Converter (ADC).